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| DFPAU-DP Floating Point Arithmetic Coprocessor Double Precision ver 3.02 OVERVIEW DFPAU-DP is a Floating Point Arithmetic Coprocessor, designed to assist CPU in performing the floating point arithmetic computations. DFPAU-DP directly replaces C software functions, by equivalent, very fast hardware operations, which significantly accelerate system performance. It doesn't require any programming, so it also doesn't require any modifications made in the main software. Everything is done automatically during software compilation by the DFPAU-DP C driver. DFPAU-DP was designed to operate with DCD's DP8051, but can also operate with any other 8-, 16- and 32-bit processor. Drivers for all popular 8051 C compilers are delivered together with the DFPAU-DP package. DFPAU-DP uses the specialized algorithms to compute math functions. It supports addition, subtraction, multiplication, division, square root, and comparison. It has built-in conversion instructions from integer type to floating point type and vice versa. The input numbers format is according to IEEE-754 standard. DFPAU-DP supports double and single precision real numbers, 8-bit, 16-bit and 32-bit integers. DFPAU-DP is prepared to use with 8-, 16- and 32-bit processors. Each floating point function can be turned on/off at configuration level providing the flexible scalability of DFPAU-DP module. It allows save silicon space and provides exact configuration required by certain application. All trademarks mentioned in this document are trademarks of their respective owners. http://www.DigitalCoreDesign.com http://www.dcd.pl DFPAU-DP is a technology independent design that can be implemented in a variety of process technologies. APPLICATIONS Math coprocessors DSP algorithms Embedded arithmetic coprocessor Fast data processing & control Copyright 1999-2007 DCD - Digital Core Design. All Rights Reserved. KEY FEATURES Direct replacement for C double, float software functions such as: +, -, *, /,==, !=,>=, <=, <, > Configurability of all available functions C interface supplied for all popular compilers: GNU C/C++, 8051 compilers No programming required IEEE-754 Double precision real format support - double type IEEE-754 Single precision real format support - float type 8-bit, 16-bit 32-bit and 52-bit integers format supported - integer types Flexible arguments and result registers location Performs the following functions: FADD, FSUB FMUL, FDIV FSQRT FXAM FUCOM FCLD, FILD DELIVERABLES Source code: VHDL Source Code or/and VERILOG Source Code or/and Encrypted Netlist or/and plain text EDIF netlist VHDL & VERILOG test bench environment Active-HDL automatic simulation macros NCSim automatic simulation macros ModelSim automatic simulation macros Tests with reference responses Technical documentation Installation notes HDL core specification Datasheet Synthesis scripts Example application Technical support IP Core implementation support 3 months maintenance - addition, subtraction - multiplication, division - square root - examine input data - comparison - 8-bit, 16-bit integer to dou- 32-bit, 52-bit integer to - double to 8-bit, 16-bi inte- double to 32-bit, 52-bit in- float to double - double to float Delivery the IP Core updates, minor and major versions changes Delivery the documentation updates Phone & email support ble FLLD, FELD double FCST, FIST ger FLST, FEST teger FFLD FFST Exceptions built-in routines Masks each exception indicator: Precision lack PE Underflow result UE Overflow result OE Invalid operand IE Division by zero ZE Denormal operand DE Fully configurable Fully synthesizable, static synchronous design with no internal tri-states All trademarks mentioned in this document are trademarks of their respective owners. http://www.DigitalCoreDesign.com http://www.dcd.pl Copyright 1999-2007 DCD - Digital Core Design. All Rights Reserved. LICENSING Comprehensible and clearly defined licensing methods without royalty fees make using of IP Core easy and simply. Single Design license allows using IP Core in single FPGA bitstream and ASIC implementation. It also permits FPGA prototyping before ASIC production. Unlimited Designs license allows using IP Core in unlimited number of FPGA bitstreams and ASIC implementations. In all cases number of IP Core instantiations within a design, and number of manufactured chips are unlimited. There is no time of use limitations. Single Design license for VHDL, Verilog source code called HDL clk rst cs PINS DESCRIPTION PIN TYPE Input Input Input Input Input Input 2 DESCRIPTION Global system clock Global system reset Chip select for read/write Data bus input Register address to read/write Data write enable datai[31:0]1 addr[4:2] we datao[31:0]1 irq Output Data bus output Output Interrupt request indicator 1 - data bus can be configured as 8-, 16- or 32- bit depends on processor's bus size 2 - address bus is aligned to work with 8- (3:0), 16(3:1) or 32- (4:2) bit processors BLOCK DIAGRAM Mantissa - performs operations on mantissa part of number. The addition, subtraction, multiplication, division, square root, comparison and conversion operations are executed in this module. It contains mantissas and work registers. datai(31:0)1 datao(31:0)1 irq Interface Mantissa Source Encrypted, or plain text EDIF called Netlist Unlimited Designs license for HDL Source Netlist Upgrade from Netlist to HDL Source Single Design to Unlimited Designs SYMBOL datai(31:0) addr(4:2) we 2 1 datao(31:0) 1 addr(4:2)2 we cs Align irq Exponent Shifter cs rst clk clk rst Control Unit Exponent - performs operations on exponent part of number. The addition, subtraction, shifting, comparison and conversion operations are executed in this module. It contains exponents and work registers. Align - performs the numbers analyze against IEEE-754 standard compliance. Information about the data classes are passed as result to appropriate internal module. Shifter - performs mantissa shifting during normalization, denormalization operations. All trademarks mentioned in this document are trademarks of their respective owners. http://www.DigitalCoreDesign.com http://www.dcd.pl Copyright 1999-2007 DCD - Digital Core Design. All Rights Reserved. Information about shifted-out bits are stored for rounding process. Control Coprocessor - manages execution of all instructions and internal operation required to execute particular function. Interface - makes interface between external device and DFPAU-DP internal 32-bit modules. It contains data, control and status registers. It can be configured to work with 8-, 16- and 32-bit processors. PERFORMANCE The following table gives a survey about the Core area and performance in the ALTERA(R) devices after Place & Route (all key features have been included): Speed Logic Cells Fmax grade CYCLONE -6 3660 79 MHz CYCLONE-II -6 3630 71 MHz STRATIX -5 3660 84 MHz STRATIX-II -3 2800 110 MHz Core performance in ALTERA(R) devices Device DFPAU-DP floating point instructions performance has been compared to standard C library functions delivered with every commercial C compiler. Each program was executed in the same system environments. Number of clock periods were measured between input data loading into work registers and output result storing after operation. The results are placed in table below. Improvement has been computed as number of: (NIOS-II CLK) divided by (NIOS-II+DFPAUDP CLK), required to execute particular instruction. IEEE-754 FP Instruction Addition Subtraction Multiplication Division Square Root Sine Cosine Tangent Arcs Tangent Average speed improvement: Improvement 12.0 11.7 10.6 15.0 21.5 11.8 10.3 10.1 14.7 13.1 More details are available in core documentation. The following table gives a survey about the 32-bit NIOS-II+DFPAU-DP performance compared to 32-bit NIOS-II. Device NIOS-II NIOS-II+DFPAU (arithmetic) NIOS-II+DFPAU (trigonometric) NIOS-II+DFPAU (overall) Improvement 1.0 14.1 11.7 13.1 All trademarks mentioned in this document are trademarks of their respective owners. http://www.DigitalCoreDesign.com http://www.dcd.pl Copyright 1999-2007 DCD - Digital Core Design. All Rights Reserved. 15 14,1 11,7 13,2 10 5 1 0 32-bit NIOS-II NIOS-II+DFPMU-DP (arithmetic) NIOS-II+DFPMU-DP (trigonometric) NIOS-II+DFPMU-DP (overall) All trademarks mentioned in this document are trademarks of their respective owners. http://www.DigitalCoreDesign.com http://www.dcd.pl Copyright 1999-2007 DCD - Digital Core Design. All Rights Reserved. CONTACTS For any modification or special request please contact to Digital Core Design or local distributors. Headquarters: Wroclawska 94 41-902 Bytom, POLAND n fo @ d c d .p l e-mail: iinfo@dcd.pl tel. fax : +48 32 282 82 66 : +48 32 282 74 37 Distributors: http://www.dcd.pl/apartn.php Please check http://www.dcd.pl/apartn.php All trademarks mentioned in this document are trademarks of their respective owners. http://www.DigitalCoreDesign.com http://www.dcd.pl Copyright 1999-2007 DCD - Digital Core Design. All Rights Reserved. |
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